The present application relates to semiconductor devices and manufacturing processes, and more particularly, to a method of reducing parasitic capacitance of transistors during the formation of interconnect structures using a subtractive etch process.
Integrated circuits (ICs) commonly use metal interconnect structures (or “lines”) to connect semiconductor devices such as, for example, transistors, on the ICs. These interconnect structures are typically formed using an additive damascene process in which a dielectric layer is patterned to include openings therein. A conductive metal, for example, copper (Cu) is subsequently deposited within the openings and thereafter any conductive metal that is located outside the openings is removed via a planarization process.
However, the conventional additive damascene process is not always compatible with the trend toward smaller feature sizes in modern complementary metal oxide semiconductor (CMOS) technology. For instance, as the line width scales, the resistivity of the metal is increased due to the small metal grain size. In general, a small grain size leads to greater grain boundaries which causes an increase in resistance in conductive metals. As a result, the IC performance is decreased. Moreover, as the circuit components become smaller, parasitic effect once considered minor become more significant. Therefore, a method that allows forming interconnect structures with reduced resistance and also allows reducing parasite capacitance that exists among various components of transistors remains needed.